The present invention relates to a process and apparatus for communicating data over a high speed parallel bus, and more particularly to a process and apparatus for communicating a random number of bytes (1 byte=8 bits) over a SCSI compatible data bus that is at least two bytes wide and operating under a proposed update of the SCSI standard.
The Small Computer System Interface (SCSI), as defined by ANSI X3.131 issued in 1986, has found wide acceptance in the computer industry. The ANSI standard defines a high speed parallel bus and the interconnections to the bus. This high speed parallel bus has a data portion and a control portion. As defined in the ANSI standard, the SCSI bus transfers parallel data words that are one byte wide. Each data byte transferred by the data portion has an associated parity bit that is transferred with it on a line of a control portion.
A very popular use of the SCSI standard by industry has been in peripherals, such as the SCSI disk controller described in U.S. Pat. No. 4,965,801 "ARCHITECTURAL ARRANGEMENT FOR A SCSI DISK CONTROLLER INTEGRATED CIRCUIT", by Keith DuLac and assigned to the assignee of the present invention. But this disk controller has only a one byte wide SCSI bus to transfer data, so its data bandwidth is not as high as it could be if it had a wider parallel data bus.
The SCSI bus and interconnect has been so well received by the computer industry that there is strong interest in the industry to update the SCSI standard to allow it to grow as computer systems have grown, and yet maintain compatibility with existing one byte SCSI equipment. To allow the SCSI bus and interconnect to grow, it has been proposed that SCSI be permitted to transfer one or more bytes at a time. This would allow SCSI bus systems keep up with advances to 32 and 64 bit processors and large (&gt;100 Megabytes) disk systems, and maintain compatibility with existing equipment.
An updated SCSI standard, proposed ANSI X3T9.2/86-109, Revision 10h dated Oct. 17, 1991, is nearing adoption by ANSI. This proposed update, referred to as SCSI-2, provides for one byte, two byte and four byte parallel words to be transferred across the SCSI data bus. SCSI-2 is so near completion that some computer systems using SCSI-2 two byte and four byte wide data buses are already being developed. Each byte of the data word has a respective parity bit associated with it that is transferred on a respective control line at the same time that its respective data byte is transferred.
Having a parallel data bus that is two bytes or four bytes wide presents some problems for a computer system that did not occur on the original one byte SCSI bus. For example, how does the computer system handle block transfers of an odd number of bytes across a SCSI-2 bus? How does the computer system handle two blocks of contiguous address data that are transferred across a SCSI-2 bus where both blocks have an odd number of bytes? Or, how does a computer system that is receiving data words that are oriented on odd addresses as word boundaries instead of even word boundaries re-orient data words that are transmitted with even address orientations?
A computer system using a SCSI-2 chip similar in architecture to the one described in U.S. Pat. No. 4,965,801 mentioned above but enlarged to electrically connect to a multiple byte data bus would be heavily burdened by a stream of instructions from system. processor to the SCSI chip that would be required to handle the possibilities that multiple byte word transfer creates. Not only would the system processor be burdened by the data instructions and manipulations required by some common multiple byte transfers over a SCSI-2 bus, but the system bus and the system direct memory access controller (DMA) would be burdened also.
It is an object of this invention to provide an integrated circuit SCSI-2 processor that combines a SCSI-2 interface protocol and data handling capability and a DMA interface protocol and data handling capability between a SCSI-2 bus and a system memory.
It is another object of the invention to provide a SCSI-2 processor that performs block transfers of an odd number of bytes without burdening a system processor with the task.
It is another object of the invention to provide a SCSI-2 processor that can perform scatter-gather memory operations without burdening a system processor with the task.